The invention relates to high precision bias voltage generating circuits, especially those useful in biasing push-pull driver circuits, diamond follower circuits, certain level shifting circuits, and certain diode-switching circuits.
There are a number of well-known circuits for biasing push-pull driver circuits that contain an NPN pullup transistor and a PNP pulldown transistor each having its emitter connected to the same output conductor. One such biasing circuit is shown in FIG. 2A, in which a diode-connected PNP transistor 43 is connected in series with a diode-connected NPN transistor 44. This series-connected pair of transistors is coupled between the base of NPN pullup transistor 12 and the base of PNP pulldown transistor 13. The current through current source 42 flows through both transistors 43 and 44, producing a voltage V.sub.b equal to V.sub.BE (43) plus V.sub.BE (44) between conductors 5 and 6, which are connected to the bases of NPN transistor 12 and PNP transistor 13. The input voltage V.sub.IN is applied to conductor 6. The prior art circuit of FIG. 2A requires operation of the diode- connected transistors with zero collector to-base voltage. For linear operation of the circuit, it is essential that the internal collector-base junction not become substantially forward biased. This requires that the internal collector resistance be small, which in turn requires relatively large emitter area and collector contact area to prevent the internal forward base-to-collector bias voltage from exceeding approximately 200 millivolts. The internal forward bias of the collector-base junction also increases the collector-base junction capacitance, contributing to degradation of the circuit's bandwidth.
FIG. 2B shows another known technique using an NPN source follower 52 to drive the base of the PNP pulldown transistor 13 and a PNP source follower 54 to drive the base of the NPN pullup transistor 12. In FIG. 2B, the difference between the output voltages of the NPN source follower 52 and the PNP source follower 54 provides a voltage Vd equal to the sum of V.sub.BE (54) and V.sub.BE (52) to bias output transistors 12 and 13. This circuit dissipates more power than is desirable because separate current sources I are required for the two source followers. Another problem with the circuit of FIG. 2B is that the emitter follower transistors are usually scaled to the output transistors to control quiescent current in the output stage. In many amplifiers, this results in a large nonlinear collector-base capacitance on the input node and causes distortion and reduced bandwidth.
FIG. 2C discloses use of a so-called "V.sub.BE multiplier" as a bias circuit coupled between the base of NPN pullup transistor 12 and PNP pulldown transistor 13. The V.sub.BE multiplier circuit produces a voltage V.sub.c between conductors 5 and 6 that is equal to the V.sub.BE voltage of NPN transistor 62 times a quantity that is a function of the resistances R of resistors 64 and 65. The V.sub.BE multiplier circuit, however, does not accurately control the bias current because the current in the V.sub.BE multiplier transistor is controlled by both the base-to-emitter voltage of the V.sub.BE multiplier transistor 62 and the resistance of the two resistors 64 and 65. Since these quantities are controlled by different process variables in the manufacture of an integrated circuit, the bias current produced by the V.sub.BE multiplier in FIG. 2C is not as accurately controlled and process-independent as is desirable.
U.S. Pat. No. 4,317,081 (Kobayashi) discloses a single ended push-pull power amplifier in which the PNP transistor Q9 has its base connected to the base of an NPN transistor Q10. The emitter of Q9 is connected to the collector of Q10 and the emitter of Q10 is connected to the collector of Q9. A resistor R5 is connected between the base and emitter of Q9 and a resistor R6 is connected between the base and emitter of Q10. This circuit is used between a bias circuit 12 and a complementary push-pull output circuit Q7,Q8 to improve high frequency performance by discharging charge stored in the output transistors Q7,Q8. The bias circuit 12 applies a bias voltage to the bases of the push-pull output circuit Q7,Q8 and across the two resistors R5 and R6 and transistors Q9 and Q10. This circuit has the disadvantage that resistors R5 and R6 require a large amount of chip area and their resistances are controlled by different process parameters than the V.sub.BE voltages of transistors Q9 and Q10. Consequently, an imbalance in the resistances of those resistors would result in large differences in the currents flowing through the two transistors, causing substantial undesired process-dependent variations in the bias voltage produced by the circuit.
It would be desirable to provide a bias circuit which provides a very precise bias voltage equal to the sum of the V.sub.BE voltages of a PNP pullup transistor and an NPN pulldown transistor with a common emitter connection. The matching of the bias voltage to the sum of the V.sub.BE voltages should be essentially independent of the saturation currents of the NPN and PNP transistors.